1. Field of the Invention
The present invention relates to the structure of a semiconductor integrated circuit, wherein a junction-type field effect transistor and a bipolar semiconductor device are formed on a single monolithic semiconductor substrate.
2. Prior Art
In a junction-type field effect transistor (hereinafter referred to J-FET) the drain current is proportional to the square of the gate voltage. In a bipolar transistor, however, collector current is exponentially proportional to base voltage. The J-FET is now used in numerous fields such as audio instrumentation. Recently, it has become necessary to form a J-FET and a bipolar transistor on a single monolithic substrate to make an integrated circuit (IC). Several attempts are now being tried to realize this kind of IC.
The merits of these attempts are as follows:
(i) the input impedance can be raised by introducing the J-FET in the IC, PA1 (ii) the input impedance of the J-FET is high and therefore amplification of the first stage of an audio amplifier is made without producing noise, PA1 (iii) it is possible to increase the degree of freedom for circuit design, reducing the number of parts for low noise and a high integration density, PA1 (iv) the required chip area and costs can be reduced as compared to a J-FET used independently from the IC, and noise generated at interconnection means etc. can be reduced.
Conventionally, only p-channel type J-FETs are used to make the IC, which comprises both the J-FET and the bipolar transistor on the single substrate, and such IC's are developed mainly for operational amplifiers. This is because an n-channel type J-FET is difficult to fabricate due to an increase of the fabrication process steps (thermal diffusion process steps). The noise characteristics of the n-channel type J-FET are not good as to be described later. Also a p-channel type J-FET can be used in an operational amplifier, for which both a positive with a negative power sources are available and the source of the p-channel type J-FET connected to the negative power source (since for a p-channel type J-FET, the gate is positive against the source).
For a usual top gate type J-FET, where a gate diffusion region is formed in an epitaxially grown layer, its channel thickness is determined by the difference between the thickness of the epitaxial layer and diffusion depth of a gate diffusion region, and this difference must be controlled very precisely.
On the other hand, the base thickness of a bipolar transistor in an IC is determined by the time period of the thermal treatment for diffusion for a base region and an emitter region (since the base thickness is the difference of depths between both diffused regions). The allotment of these time periods delicately determines the base thickness giving rise to a suitable value of current amplification factor h.sub.fe. Accordingly, the precise control for the channel thickness of the J-FET can not be coexistent with the thermal treatment condition since the channel thickness usually changes during the thermal treatment. It is therefore quite difficult to make the IC containing both a J-FET and a bipolar transistor in a single substrate.
When forming the J-FET together with the bipolar transistor in the IC, the construction with a back gate structure shown in FIG. 1 has been employed. FIG. 1 shows a p-channel type J-FET which is conventionally formed in an integrated circuit together with a bipolar transistor. That is, the J-FET with a surface channel and of the back gate structure is employed for the IC, since, in the fabrication process comprising such J-FET, it is possible to form a channel region without using thermal treatment of such high temperature as to change the base thickness of the bipolar transistor and therefore it is possible to obtain stable DC characteristics.
FIG. 1 shows a general structure of the back gate type J-FET. A back gate region 2 of an n-type epitaxial layer having a bulk resistivity of 1-3.OMEGA.. cm is formed on a p-type substrate 1. A source region 3 and a drain region 4 of p.sup.+ -type diffused regions are simultaneously formed with forming of a base region of a bipolar transistor (not shown in FIG. 1) which is also formed in the n-type epitaxial layer 2. An n.sup.+ -type diffused gate contact region 5 is also fomed in the n-type epitaxial layer 2. A p-type channel region 6 of a low concentration is formed so as to have a precise depth by an ion implantation through the upper surface of the epitaxial layer 2. A thermally grown oxide film 7 and metal electrodes 8.sub.S, 8.sub.D and 8.sub.G for the source 3, the drain 4 and the gate 5, respectively are formed on specified parts of the substrate as shown in FIG. 1.
Operation of this J-FET is based on the function that conductance of the channel region 6 is controlled by a voltage applied to the gate region 2. Namely, the conductance control is made by impressing a bias voltage through the gate electrode 8.sub.G to a part of the back gate region 2 which is under the channel region 6.
Since the channel region 6 of this kind J-FET is formed at the surface, the thickness and the impurity concentration of the channel region 6 are not strongly affected by the thickness and the impurity concentration of the epitaxial layer 2. This is a merit for the manufacturing and they are determined almost solely by an amount of impurities doped through the surface. Therefore, the channel region 6 of a low resistivity value can be precisely formed by, for example, the ion implantation.
But the device shown in FIG. 1 has the following significant shortcomings. Since carriers running in the channel region 6 are controlled by the gate bias voltage given from the bottom of the channel region 6, the carriers run only near the surface of the channel region 6, resulting in noise troubles. This is attributed to several noise causes such as recombination and generation of charges by the surface states at the interface between the oxide film 7 and the channel region 6, and defects at the surface due to distortions made during processing.
In order to overcome these shortcomings, several alteration can be made to prevent the carriers from running at the surface of the channel region 6.
For example, FIG. 2 shows a J-FET, wherein an electrode 8ch for applying voltage is formed on a thermally grown oxide film 7 at the surface of a channel region 6. Electrode 8ch, can create electrically an inversion region 9 at the surface of channel region 6 thereby preventing carriers from flowing at the interface of the channel region 6 and the thermally grown oxide film 7, thereby to reduce reciprocal--frequency (1/f) noise. This is caused by fluctuation of carriers triggered by surface states at the interface of the channel region 6 and the thermally grown oxide film 7. The lower the frequency is, the larger this noise is. The 1/f noise is a nightmare in audio, data-acquisition, instrumentation and preamp work. Although the inversion region 9 can be formed in the channel region 6 of the J-FET, a high voltage of more than 10 V is usually necessary depending on the thickness of the thermally grown oxide film 7. And this is not suitable for usual IC's.
A second possibility is to form a high resistive layer such as an intrinsic semiconductor layer (i-type layer) at the surface of a channel region 6 in order to eliminate the flow of surface carriers of the channel region 6. In this method the carriers easily move from the channel region 6 to the i-type layer since the impurity concentration of the i-type layer is low, the recombination in the i-type layer is carried out by these mobile carriers and noise sources at the surface still exist, therefore no drastical reduction of noise can be expected.
A third possibility, conceived by the inventors but not previously disclosed to the public, is to form an n-type layer over the entire surface of the channel region 6. In this case the n-type layer at the surface must have a low impurity concentration so that the breakdown voltage between the source and the drain is not reduced. A J-FET with this n-type layer of low impurity concentration also suffers from surface recombination noise similar to that of the above-mentioned i-type layer. And besides, control of the depth of the channel is difficult and values of saturation drain current I.sub.DSS vary much in a single lot, since the depletion layer of the p-n junction at the interface between the n-type layer and the channel region 6 spreads to both the n-type surface layer and the channel region 6. If an n.sup.+ -type layer of a high impurity concentration is formed over the entire surface of the surface channel region 6, the surface recombination noise effect would disappear and the channel depth control could be easily made, because the depletion layer spreads to only the direction of the channel region 6. However the breakdown voltage between the source 3 and the drain 4 becomes lower, making the device unpractical.
A resistor region can be formed in the epitaxial layer 2 simultaneously with the surface channel of the J-FET, by utilizing the ion implantation. The resistor for this purpose should preferably has a good linearity with respect to applied voltage, and therefore the pinch off voltage of the resistor should preferably be large. On the other hand, the pinch off voltage for the J-FET should be small contrary to the case of the resistor. Accordingly, it is extremely difficult to simultaneously form the resistor region and the surface channel region of the J-FET in a monolithic semiconductor IC.
Furthermore, this IC has the following problem. In general, the bipolar transistor formed in an IC is of n-p-n type, and it is preferable that such an IC be operated by a single-voltage source from a positive terminal and a negative terminal. For example, J-FET(s) in an IC to be used in audio appliances such as a tape recorder should preferably be operable with the single-voltage source. In such an IC, to be operated with a low and single-voltage source, the J-FET(s), which is combined with the n-p-n transistor(s) should be of n-channel type. In order to form such n-channel J-FET(s) with a back-gate in the IC, it is necessary to form a p-type well to become a gate region in the n-type epitaxial region. Therefore, the IC should have the construction as shown in FIG. 3.
Namely, FIG. 3 shows a fourth possibility, conceived by the inventors but not previously disclosed to the public, a fourth preceding concept on the way to the present invention. The device of FIG. 3 has such construction that, based on the fundamental construction of FIG. 1, an n-channel J-FET NCHFT formed in a p-type well 11a, a bipolar transistor BPTR and a resistor RST are formed on a monolithic substrate 1. As shown in FIG. 3, on a p-type semiconductor substrate 1 having n-type buried regions 10a, 10b and 10c, an n-type epitaxial layer 2 is formed. Then, p.sup.+ -type isolation regions 29 are formed in the n-type epitaxial layer 2, and a p-type well 11a to become a back gate and a p-type well 11b to embrace a resistor region are formed in the n-type epitaxial layer 2. A p.sup.+ -type gate contact region 12 is formed by diffusion in the p-type well 11a simultaneously with forming by diffusion of a p.sup.+ -type base region 13 in the collector region 2' of the bipolar transistor BPTR. An n.sup.+ -type source region 14 and an n.sup.+ -type drain region 15 of the n-channel J-FET NCHFT, an n.sup.+ -type emitter region 18 of the bipolar transistor BPTR, and an n-type resistor contact regions 16 and 17 in the resistor part RST are formed, all at the same time, by a diffusion. An n-type surface channel region 19 extending between the source region 14 and the drain region 15 and an n-type resistor region 20 extending between the contact regions 16 and 17 are formed all at the same time by a diffusion. Then metal electrodes 21, 22, 23, 24 and 25 for the source region, the drain region, the gate region, the emitter region and the base region, respectively and metal electrodes 26 and 27 for the resistor region 20 are formed by a known method. Numeral 28 designates a know insulating layer of, for example an oxide film. Numeral 29 are p.sup.+ -type isolation regions. And a metal electrode 30 as a MOS gate electrode is formed on the gate oxide film 28' on the surface channel region 19.
In the IC of FIG. 3, the step of forming the p-type wells 11a and 11b are carefully made in order to obtain a sufficient depth so as to include the gate contact region 12, which is diffused simultaneously with diffusion of the base region 13 of a specified depth, that should be larger than that of the emitter region 18. After the step of forming the p-type wells 11a and 11b, the steps for forming the regions in the resistor part RST can be made simultaneously with those for the n-channel J-FET part NCHFT. According to the abovementioned construction, the inventors obtained satisfactory values of DC parameters of the J-FET such as a pinch off voltage V.sub.p, drain saturation current I.sub.DSS and transconductance g.sub.m and also of current gain h.sub.fe. The collector-base breakdown voltage with open base V.sub.CBO and collector-emitter breakdown voltage with open base V.sub.CEO, with an IC comprising a J-FET wherein sheet resistance is several K.OMEGA. and channel thickness is about 0.1 to 0.4.mu.m is also satisfactory.
However, the inventors found that the device of FIG. 3 has considerably large noise for all frequency range as shown by the curve I of FIG. 4, and especially, its reciprocal frequency noise is so large that in some IC chips, the equivalent noise voltage for around 10 Hz exceeds 1 .mu.V/.sqroot. Hz, and is worse than that of p-channel J-FET. Apparently such large noise is produced by the carriers at the channel surface and resultant recombination and generation of electric charges at traps existing at the interface between the oxide film 28' and the surface channel region 19. Thus the noise is produced by the surface states. In FIG. 4, which shows relations between the equivalent input voltage e.sub.n (nV/.sqroot.Hz) and frequency, the other curve II shows the noise characteristic of the p-channel FET shown in FIG. 2. As is apparent from a comparison of the curves I and II of FIG. 4, even though having a MOS gate, the n-channel type IC (curve I) of FIG. 3 has poorer noise characteristic than that of the p-channel type (curve II), especially in the low frequency range. The reason for this is not clear theoretically, but may be related to the kinds of carriers in the channel. Thus, surface channel J-FETS have poor noise characteristics.
Furthermore, if the n-channel J-FET part NCHFT of the IC of FIG. 3 has a low pinch off voltage V.sub.p of about IV, then at application of a voltage of about the value V.sub.p to the resistor part RST, the resistor part saturates, instead of having an ohmic linear characteristic such a saturated non-linear characteristic at the application of such a low voltage is an adverse characteristic which limits the utility of the IC. On the other hand, if resistor part RST of the IC of FIG. 3 is made to have a high saturation voltage by making the depth of the diffused regions 19 and 20 to be over 4 .mu.m and the sheet resistance of the diffused regions to be several K.OMEGA., then the saturation point of voltage-current characteristic of the resistor part RST can be much improved but the pinch off voltage V.sub.p of the J-FET part NCHFT becomes extraordinary high thereby making the performance of the J-FET poor. Also the carriers will flow at the substrate surface part raising the reciprocal frequency noise.
Other types of resistors can be made in the ICs simultaneously with forming of the base region or the emitter region. But the sheet resistance of these regions range from 10 .OMEGA. to 300 .OMEGA., and therefore, the resistance obtained is not sufficient. A squeeze resistor, which is made by utilizing a depletion layer of the base formed between the emitter and the base, can be of high resistance. However, the squeeze resistor has poor ohmic linearity and a low breakdown voltage V.sub.CEO of about 5 to 6 V, since the impurity concentration of the base region is high.
As has been elucidated, as a result of the abovementioned research through several possibilities of the conceived construction, the inventors found that, (1) in order to decrease scattering of the DC characteristics, the depth of the channel and the depth of the gate region should be made small, (2) the noise, especially 1/f noise, becomes large when the carriers move at the surface part and (3) even if a MOS gate is provided, a high voltage is necessary. Furthermore, in order to obtain a FET in an IC comprising a combination of bipolar device(s) and J-FET(s) with stable DC characteristics, a back gate type construction is necessary, because high manufacturing temperatures are unnecessary; but this back-gate type device has poor noise characteristics, especially of large 1/f noise, and moreover, it is difficult to obtain an IC with a resistor part of good ohmic characteristic required for use in audio appliances and the like.